In modern semiconductor memories, the desire to lower power consumption has resulted in a decrease in the magnitude of a supply voltage V.sub.CC which provides power to the memories. All electronic systems typically benefit from lower power consumption, particularly portable systems which are battery powered. When the supply voltage V.sub.CC decreases, reference voltage circuitry in the memory that develops reference voltages having a values which are a function of the supply voltage accordingly develop reference voltages having different values. For example, in many semiconductor memories digit lines are biased and equilibrated to a voltage equal to the supply voltage V.sub.CC divided by two. In this situation, a change in the supply voltage from 5 volts to 3.3 volts results in the bias voltage changing from 2.5 volts to 1.65 volts. Such a decrease in the bias voltage may affect the operation of circuitry in the memory that utilizes the bias voltage during operation.
One type of circuit that may be affected by a decrease in the bias voltage is a sense amplifier circuit. In a typical dynamic random access memory ("DRAM"), a sense amplifier circuit senses data stored in a memory cell by sensing a voltage differential between a pair of complementary digit lines associated with the memory cell as known in the art. The sense amplifier circuit senses the voltage differential and drives the digit line at the higher voltage to approximately the supply voltage V.sub.CC and the digit line at the lower voltage to approximately zero volts. Typically, the sense amplifier circuit includes NMOS and PMOS transistors coupled between the digit lines. When the supply voltage V.sub.CC decreases, the threshold voltages V.sub.T of these transistors may prevent the sense amplifier circuit from driving the digit lines to the desired voltages as will be explained in more detail below.
FIG. 1 is a schematic of a conventional sense amplifier 10 which senses the data stored in a memory cell 12 coupled to one of a pair of complementary digit lines DL and DL. A sense amplifier drive circuit 14 activates the sense amplifier 10 in response to a pair of activation signals NLAT and PSENSE, and a bias and equilibration circuit 16 biases and equilibrates the voltages on the digit lines DL and DL to a bias voltage V.sub.CC /2 in response to an equilibration signal EQ. The memory cell 12 is a conventional DRAM memory cell including an access transistor 18 receiving a word line signal WL and operable, when activated, to couple one plate of a storage capacitor 20 to the digit line DL. Data is stored in the memory cell 12 in the form of a charge on the storage capacitor 120, which receives a cell plate voltage V.sub.CC /2 on its other plate. Typically, the memory cell 12 stores a binary 1 as a charge on the storage capacitor 20 causing the voltage on the plate coupled to the access transistor 18 to equal V.sub.CC, and a binary 0 as a charge causing the same voltage to equal zero volts.
The sense amplifier 10 is a conventional sense amplifier including a pair of NMOS transistors 22 and 24 and a pair of PMOS transistors 26 and 28 coupled between a pair of data terminals 27 and 29. A pair of isolation transistors 31 and 33 couple the data terminals 27 and 29 to the complementary digit lines DL and DL, respectively, in response to an isolation signal ISO. The interconnected sources of the transistors 22 and 24 form an activation node 30, and the interconnected sources of the transistors 26 and 28 form an activation node 32. An NMOS drive transistor 34 in the drive circuit 14 couples the activation node 30 to ground in response to the signal NLAT received on it gate, and a PMOS drive transistor 36 couples the activation node 32 to the supply voltage V.sub.CC in response to the signal PSENSE received on its gate. The bias and equilibration circuit 16 includes an NMOS equilibration transistor 38 that equalizes the voltages on the digit lines DL and DL and two NMOS bias transistors 40 and 42 that drive the voltages on the digit lines DL and DL, respectively, to the bias voltage V.sub.CC /2, all of these transistors being activated by the equilibration signal EQ received on their gates.
In operation, before data is read from the memory cell 12, a control circuit (not shown in FIG. 1) drives the signal EQ active, and drives the signals WL, ISO, NLAT, and PSENSE inactive. In the following description, the signal ISO remains inactive so the digit lines DL, DL remain coupled to the data terminals 27, 29, but one skilled in the art will realize the signal ISO may be used to selectively activate the transistors 31, 33 to enable sharing of the sense amplifier 10 by digit lines in adjacent memory-cell arrays (not shown in FIG. 1). In response to the active signal EQ, the bias and equilibration circuit 16 biases the voltages on the digit lines DL and DL to the bias voltage V.sub.CC /2. For the purposes of the following description, assume the memory cell 12 stores a binary 1 so the voltage on the plate of the storage capacitor 20 coupled to the access transistor 18 is at approximately V.sub.CC. After the voltages on the digit lines DL and DL have been biased at V.sub.CC /2, the control circuit deactivates the equilibration signal EQ. The control circuit thereafter activates the word line signal WL and charge flows from the storage capacitor 20 through the activated access transistor 18 and onto the digit line DL. In response to the charge transferred from the storage capacitor 20 to the digit line DL, the voltage on the digit line DL increases slightly above the bias voltage V.sub.CC /2. At this point, a voltage differential exists between the digit lines DL and DL since the voltage on the digit line DL is slightly greater than the bias voltage V.sub.CC /2 present on the digit line DL.
After the voltage differential has developed on the digit lines DL and DL, the control circuit activates the signal NLAT turning ON the drive transistor 34 and thereby coupling the activation node 30 to ground. When the drive transistor 34 couples the voltage on the activation node 30 to approximately ground, the transistors 22 and 24 turn ON. The transistor 24 turns ON harder than the transistor 22 due to the higher voltage on the digit line DL applied to its gate. As the transistor 24 turns ON, the voltage on the digit line DL goes to ground as charge flows from the digit line DL through the transistor 24 and through the drive transistor 34 to ground. The transistor 22 turns OFF as the voltage on the digit line DL applied to its gate goes to ground. In this way, the NMOS transistors 22 and 24 turn OFF and ON, respectively, driving the voltage on the digit line DL to ground. The NMOS transistors 22 and 24 are typically activated before the PMOS transistors 26 and 28 because they have lower threshold voltages V.sub.T as will be discussed in more detail below.
The control circuit thereafter activates the signal PSENSE turning ON the drive transistor 36 and thereby coupling the activation node 32 to the supply voltage V.sub.CC. When the drive transistor 36 couples the voltage on the activation node 32 to approximately V.sub.CC, the transistors 26 and 28 turn ON. The transistor 26 turns ON much harder than the transistor 28 due to the voltage of approximately zero volts on the digit line DL applied to its gate. As the transistor 26 turns ON, the voltage on the digit line DL goes to the supply voltage V.sub.CC as charge flows from the supply voltage V.sub.CC through the drive transistor 36 and through the transistor 26 to the digit line DL. In this way, the transistors 26 and 28 turn ON and OFF, respectively, driving the voltage on the digit line DL to the supply voltage V.sub.CC. The sense amplifier 10 has at this point driven the voltages on the digit lines DL and DL high and low, respectively, corresponding to the binary 1 stored in the memory cell 12.
The schematic of FIG. 1 illustrates the single sense amplifier 10 coupled to the drive circuit 14. In a typical DRAM, however, the drive circuit 14 may be coupled to the nodes 30 and 32 of hundreds or even thousands of sense amplifiers 10 depending on the number of columns of memory cells in a memory-cell array. When thousands of activation nodes 30 are coupled to the single drive transistor 34, current flows from thousands of digit lines DL through the associated transistors 24 and then through the drive transistor 34. The activated drive transistor 34 presents a source-to-drain resistance which, although relatively small, may result in significant voltage drop across the transistor 34 due to the current from the thousands of digit lines DL. The voltage drop across the drive transistor 34 corresponds to the voltage on node 30 and may not exceed a maximum allowable voltage, as will be explained in more detail below.
In the sense amplifier 10, the difference between the voltage on the digit line DL applied to the gate of the transistor 24 and the voltage on the node 30 corresponds to the gate-to-source voltage of the transistor 24. The gate-to-source voltage of the transistor 24 must be greater than the threshold voltage V.sub.T to turn ON the transistor, as known for MOS transistors. As previously explained, when thousands of transistors 24 are activated, the voltage drop on node 30 may rise above ground due to the source-to-drain resistance of the drive transistor 34. If the voltage on the node 30 becomes greater than the voltage on the digit line DL minus the threshold voltage V.sub.T, the transistor 24 turns OFF because its gate-to-source voltage is less than the threshold voltage V.sub.T. For proper operation of the sense amplifier 10, the transistor 24 must remain active to drive the voltage on the digit line DL to ground. The same potential problem exists for the transistor 22, but typically not for the transistors 26 and 28 since the activated one of these transistors has approximately zero volts applied to its gate as a result of one of the transistors 22 and 24 being activated first. The zero volts on the gate of the activated one of the transistors 26 and 28 typically ensures a gate-to-source voltage greater than V.sub.T even for relatively large voltage drops across the drive transistor 36.
The maximum voltage that can develop on the node 30 without turning OFF the transistor 24 is a function of the magnitude of the bias voltage V.sub.CC /2, which, in turn, is a function of the magnitude of the supply voltage V.sub.CC. For example, if the supply voltage V.sub.CC equals 5 volts and the threshold voltage V.sub.T equals 0.7 volts, the maximum voltage allowable on the node 30 equals 2.5 volts minus 0.7 volts or 1.8 volts. When the supply voltage V.sub.CC is 3.3 volts, the maximum voltage allowable on the node 30 equals 1.65 volts minus 0.7 volts or 0.95 volts. Thus, as the supply voltage V.sub.CC decreases the maximum voltage allowable on the node 30 decreases accordingly.
The source-to-drain resistance and resulting voltage drop across the drive transistor 34 becomes more critical at low supply voltages V.sub.CC because the maximum voltage allowable on the node 30 decreases as the supply voltage V.sub.CC decreases. One way to reduce the voltage drop across the drive transistor 34 is to increase the physical dimensions of the drive transistor and thereby reduce its resistance. This approach is limited, however, by physical space constraints on the semiconductor substrate in which the DRAM is formed. The drive transistors 34 and 36 are typically formed in gap-cell regions on the semiconductor substrate defined between adjacent banks of sense amplifiers at the corners of memory-cell arrays as understood by one skilled in the art. The size of the gap-cell regions limits the maximum physical dimensions of the drive transistors. Moreover, in modern DRAMs the size of the gap-cell regions is decreasing in response to corresponding decreases in the size of other circuitry on the DRAM resulting, in part, from advances in semiconductor process technology.
There is a need for a sense amplifier drive circuit that enables sense amplifier circuits to quickly and reliably sense data stored in addressed memory cells in a semiconductor memory having a reduced supply voltage.